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Digital IC Design Engineer
Are you a Digital IC Design Engineer with experience in RTL design, synthesis and DFT for mixed-signal chips? Do you want to play a key role in building next generation Wi-Fi chips that will enable IoT? Keen to make a real difference in a VC-backed high growth company while working in a dynamic & fun environment? Then join Australia’s fastest growing semiconductor company What we’re looking for (qualifications and experience): MSc in Electrical / Electronics / Communication Engineering or Computer Science Digital design experience with 3 years relevant industry experience A deep understanding of digital design fundamentals including low power and multi-clock-domain design for mass-produced, mixed-signal chips Experience with digital synthesis tools targeting low power, mixed-signal applications on modern technology nodes Experience with synthesis tools Experience analyzing and optimizing a design’s timing and power characteristics Experience integrating and verifying DFT infrastructure such as logic scan, boundary scan and MBIST using industry standard tools such as Mentor Tessent, Cadence Modus or Synopsys TestMAX Experience with development and debugging of digital designs from RTL design through to SDF-annotated gatesims A good understanding of embedded processor systems, familiarity with RISC-V is a plus A solid understanding of mixed signal ASIC design and simulation, experience with AMS simulation is a plus Hands-on experience with the Cadence or Synopsys simulation suite Hands-on experience with Linux development environment staples Experience using the git revision control tool Ability to document - and keep updated - instructions on running and debugging flows Responsibilities include (tasks and duties): Working within the digital team on block design and verification Developing and running digital synthesis flow to deliver netlists to backend Maintaining the DFT infrastructure and extending where necessary Interacting with the frontend, analog and backend team to get the design through to tapeout whilst meeting performance and power metrics Developing chip infrastructure verification at RTL and gate level Assisting with bring-up of silicon in the lab What we offer: Competitive salary excellent stock option package Healthy work environment with sit/stand desks and large screens Newly fitted-out offices, with a relaxed, friendly work environment If you are interested, apply online and tell us why you should become our Digital IC Design engineer at Morse Micro..